Phase interpolators are used to generate clock signals with an adjustable phase, which are used for example in communications devices within the context of clock and data recovery (CDR). Such phase interpolators are known for example from US 2003/0002607 A1 or from EP 0 909 035 A2.
The mode of operation of such phase interpolators will be explained hereinafter with the aid of FIGS. 5-8.
FIG. 5 shows in this connection a block diagram of a phase interpolator 21. Two input clock signals s and c are in this connection fed to the phase interpolator 21. The input clock signals have the same frequency and amplitude as well as a phase difference of 90° (π/2). In addition a control signal cnt is fed to the phase interpolator 21. Depending on the control signal cnt the phase interpolator 21 generates from the input clock signals s and c an output clock signal o whose phase lies between the phases of the input clock signals s and c. Phase interpolators are also known in which the phase difference between the input clock signals s and c differs from 90°, or in which more than 2, in particular 4, input clock signals are used in order to be able to generate an output clock signal o that has an arbitrary phase between 0° and 360°. The action of the phase interpolator 21 is illustrated in time representation in FIG. 6. The input clock signals c and s have a phase difference 22 of for example 90°, and the output clock signal o has, with respect to the input clock signal c, a phase difference 23 that is adjusted depending on the control signal cnt.
This state of affairs is illustrated again in phase representation in FIG. 7. The arrows represent in this connection so-called phasors, and the direction of the arrow corresponds to the phase of the corresponding signal. The arrows are denoted by P(s), P(o) and P(c) for the phasors of the corresponding signal s, o and c. P(o) is in this connection a function f of the control signal cnt.
A circuit configuration of such a phase interpolator is shown diagrammatically in FIG. 8. This phase interpolator 21 is designed as a difference interpolator, in other words the input clock signals are difference signals with the components s, s and c, c, while the output clock signal is a difference signal with components o, o.
The input clock signals are in each case fed to a difference amplifier, wherein the difference amplifier for the input clock signal s, s includes transistors T5 and T6 and a power source 10, while the difference amplifier for the input clock signal c, c includes transistors T7 and T8 as well as a power source 11. The difference amplifiers comprise common output load resistors L1, L2, which results in a summation of the outputs of the difference amplifiers.
In FIG. 8 in addition reference numeral 17 denotes an earth potential and 18 denotes a further defined potential, for example a positive supply voltage.
The control signal cnt controls the power sources 10 and 11 in order to vary the currents Is and Ic generated by them. This may be achieved in such a way that the sum of the currents Is and Ic remains constant. By varying the currents Is and Ic a weighting of the input clock signals s, s and c, c is carried out, whereby the phase of the output clock signal o, o is altered.
Such known phase interpolators are based on the following equation:
                                          A            ·                          sin              ⁡                              (                                  2                  ⁢                  π                  ⁢                                                                          ⁢                  ft                                )                                              +                                    (                              1                -                A                            )                        ⁢                          cos              ⁡                              (                                  2                  ⁢                  π                  ⁢                                                                          ⁢                  ft                                )                                                    =                                                            2                ⁢                                  A                  2                                            -                              2                ⁢                A                            +              1                                ⁢                      cos            ⁡                          (                                                2                  ⁢                  π                  ⁢                                                                          ⁢                  ft                                +                                  arctan                  ⁡                                      (                                          A                                              1                        -                        A                                                              )                                                              )                                                          (        1        )            
The formula (1) states that with two sinusoidal input clock signals with 90° phase difference (sin(2πft) and cos(2πft)) of frequency f, which are weighted with weighting factors A and 1-A and added, an output clock signal is generated that has a phase difference of arctan (A/1-A) compared to the cosine input clock signal, arctan being in this connection the arc tangent. Similar formulae may be derived for sinusoidal input clock signals that have a phase difference that is not equal to 90°. The value of the weighting factor A is adjusted in FIG. 8 by the control signal cnt, in which connection the control signal cnt may be a digital or analogue signal.
Equation (1) applies however only to sinusoidal signals. If the input clock signals are not sinusoidal, the dependence of the adjusted phase on the control signal cnt and on the weighting factor A is virtually impossible to calculate. In addition, in this case the output clock signal o will have a distorted waveform. This applies all the more so the greater the energy of the input clock signals in higher harmonics (for example when considering the Fourier resolution).
Conventional phase detectors must therefore satisfy two conditions: on the one hand the difference pair of transistors T5, T6 and T7, T8 must be operated in a range that is as linear as possible, which influences the necessary biaser voltage and the required input amplitude of the input clock signals s, c. On the other hand the input clock signals must not have any substantial energy in higher order harmonics, in other words they must be sinusoidal or approximately sinusoidal.
A further requirement for highly versatile phase interpolators is that they can process input clock signals with different timing (clock pulse) frequencies.
A conventional phase interpolator with which these requirements can be met is illustrated diagrammatically in FIG. 9. In this connection the input clock signals s and c are first of all fed to a signal shaping device 24, which comprises a first filter 25 for the input clock signal c and a second filter 26 for the input clock signal s. These filters are designed so as to damp higher harmonic components in the input clock signals s and c, and to match the amplitudes of the input clock signals s and c in such a way that for example the difference pair of transistors of FIG. 8 can be operated in an at least approximately linear range. The filtered input clock signals s and c generated in this way are fed to the actual phase interpolator 27, which is shown here only diagrammatically. It may for example be realised substantially like the phase interpolator 21 of FIG. 8. As shown in FIG. 9, the filtered input clock signals s and c are multiplied in multipliers 28 and 29 with weighting factors A and 1-A, and are added in an adder 30, the value A being adjusted by the control signal cnt. The intermediate clock signal o formed in this way is then preferably fed to a third filter 31, in which remaining distortions, for example of the waveform, are damped in order to generate the output clock signal o.
The filters 25, 26 and 31 are in this connection relatively complicated in design and implementation and are therefore expensive. In addition the filters must be programmable if input clock signals with different frequencies are to be processed. Also, the first filter 25 and the second filter 26 must be tuned to one another in order to generate filtered input clock signals s and c that correspond as well as possible to the requirements of formula (1).